Research Proposal: Register Allocation for Irregular Architectures

Register allocation is one of the most important optimizations a compiler performs and is becoming all the more important as the gap between processor speeds and memory access times widens. Correspondingly, a lot of effort has been spent attempting to improve traditional allocators. However, most of these attempts dealt with regular, RISC-like architectures. Published attempts to make algorithms applicable to architectures that are irregular in their use of registers have yielded several incompatible extensions that handle only a small subset of the irregularities seen in modern architectures (or so say Smith and Holloway [12]). Irregular architectures, epitomized by IA32, may have such features as register pairing (where a value must be stored in two adjacent registers), subword registers (where a value is stored and accessed in only part of a register), and register classes (where instructions can only use a subset of the total registers). In addition to the ubiquitous x86 architecture, features of irregular architectures are wide spread in embedded architectures. The Starcore, MCore, 68k, and ColdFire processors have address/data register banks and instructions are restricted in what class of register they may use. The x86 also restricts what sort of registers specific instructions can use, but not so cleanly. PA-RISC and SPARC processors use register pairing to create double valued floating point registers and most software implementations of 64 bit long longs use paired integer registers. The Broadcom Firepath, I think, implements 64 bit integers in hardware using paired integer registers. Many embedded processors, especially those with DSP connections, provide support for subword register accesses. The problem I would (very much so) like to work on is developing new algorithms that are demonstrably better than existing approaches for targeting irregular architectures in an embedded space. This means the algorithms would fully exploit the irregularities of the architecture (rather than just cope with them) and, in addition to optimizing for speed, optimize for code size. Because of the irregularities of register usage (in particular, the prevalence of addressing modes in CISC architectures), minimizing the number of spills is not equivalent to minimizing code size (a distinction I’ve yet to see addressed in the literature).